Switching aid circuit for a logic circuit

ABSTRACT

The invention concerns a switching circuit ( 20 ) adapted to generate a pulse when there occurs a rising edge of a signal applied on an input terminal (CTRL), comprising: a first NPN type bipolar transistor (TN 2 ) whereof the transmitter is connected to the input terminal; a second transistor (TP 2 ) whereof a control electrode is connected, through a first resistor (Re 2 ), to the input terminal, the base of the first transistor being connected to a supply potential (VDD) by the second transistor in series with a second resistor (Rp 2 ); and a third transistor (TN 3 ) connecting an output terminal ( 22 ) of the switching circuit to a reference potential (GND) and whereof a control electrode is connected to the collector of the first transistor (TN 2 ).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of electronic circuitsproviding or exploiting a logic signal.

According to a first aspect, the present invention more specificallyrelates to the forming of a fast logic circuit, for example implementinga non-inverting function. This type of circuit is, for example, used toadapt the level of a logic input signal and is generally designated as abuffer.

2. Discussion of the Related Art

FIG. 1 shows the conventional symbol of such a logic circuit. Circuit 1includes two supply terminals 2, 3 respectively connected to voltagesVDD and GND, the latter generally representing the ground. An inputterminal 4 of circuit 1 receives a logic signal IN. Circuit 1 provides,on an output terminal 5, a signal OUT having the same state as inputsignal IN.

FIG. 2 shows an example of an internal structure of a non-invertinglogic circuit 1 in bipolar technology. This circuit essentially includestwo transistors, TP1 of PNP type and TN1 of NPN type. Transistor TP1 isthe input transistor. Its base is connected to terminal 4 by an inputresistor Re1. The emitter of transistor TP1 is connected, by a biasingresistor Rp1, to terminal 2 at voltage VDD. The collector of transistorTP1 is connected to the base of transistor TN1. The emitter oftransistor TN1 is connected to ground terminal 3. The collector oftransistor TN1 forms output 5 terminal of circuit 1 and is connected, bya resistor Rn, to terminal 2.

The static operation of circuit 1 is the following. If input signal INis low (ground GND), transistor TP1 is on. Transistor TN1 receives abase current. It is thus also on, and output signal OUT is also low. Ifthe input signal is high (for example, voltage VDD), transistor TP1 isoff. No base current is provided to transistor TN1, which is accordinglyalso off. Output signal OUT then is high, a current flowing throughresistor Rn.

FIGS. 3A and 3B illustrate, with timing diagrams, the dynamic operationof the circuit of FIG. 1. FIG. 3A shows an example of the course ofinput signal IN. FIG. 3B illustrates the corresponding course of outputsignal OUT.

It is assumed that initially, signal IN is low and that it switches to ahigh state (voltage V1) at a time t1. The level of signal IN may bedifferent from voltage VDD provided that it is (neglecting the voltagedrop in resistor Re1) greater than VDD-VbeP, where VbeP represents thebase-emitter voltage of transistor TP1 (approximately 0.6 V). Signal OUTtakes a certain time to reach the high level (VDD, neglecting thevoltage drop in resistor Rn). The time of switching to the high state(times t1 to t2) essentially depends on the time taken by outputtransistor TN1 to desaturate. Indeed, when transistor TP1 turns off,charges remain accumulated in the base of transistor TN1 and a certaintime is necessary to evacuate them by leakage currents.

The desaturation time of transistor TN1 also depends on:

-   -   the output impedance of circuit 1, which cannot be controlled in        the forming of the logic circuit itself;    -   the time taken by transistor TP1 to desaturate by evacuating the        charges from its collector into the base of transistor TN1; and    -   the base current received by transistors TN1 and TP1 upon        switching to the low state. The greater these currents, the more        time it takes for the transistors to desaturate.

In FIG. 3A, it is assumed that signal IN switches low at a time t3. Thecircuit switching is fast in this way and signal OUT reaches the lowstate at a time t4 close to time t3. Generally the time of switching tothe low state is negligible (shorter than 100 nanoseconds). However, theoutput signal rise time is relatively long, for example, on the order ofone microsecond.

A conventional solution to accelerate the rise time is to decrease thebase current injected into transistor TN1 upon switching to the lowstate. For this purpose, the gain of transistor TP1 is decreased or itsbiasing resistance Rp1 is increased. However, the base current oftransistor TN1 must respect the condition of being sufficient to enableits saturating, failing which the switching to the low state will notoccur. Further, a significant base current enables fast switching to thehigh state. Accordingly, a compromise providing the above switchingtimes must most often be made.

Another solution is to provide an additional resistor between the baseand the emitter of transistor TN1. However, this solution only has alimited effect since the value of this resistance must still enablesaturation of transistor TN1 upon switching to the low state. Further,it causes additional power consumption.

In some applications (for example, in applications where the inputterminal may remain unconnected), it is generally desired to minimizethe circuit power consumption when the input is high or unconnected. Inthe circuit of FIG. 2, this condition is fulfilled by the fact that, inthe high state, both transistors TP1 and TN1 are off, the powerconsumption being then limited to that of resistor Rn.

SUMMARY OF THE INVENTION

According to its first aspect, the present invention aims at overcomingat least one of the disadvantages of a logic circuit implementing aconventional non-inverting function. The present invention aims, inparticular, at improving the response time of such a logic circuit.

The present invention also aims at providing such a logic circuit thatgenerates no additional power consumption when the input terminal ishigh or unconnected.

The present invention further aims at providing a solution which iscompatible with a low supply voltage (typically, under 2 V).

According to a second aspect, the present invention aims at providing acircuit exploiting a logic signal for generating a voltage pulse ofpredetermined duration upon occurrence of a square pulse of this logicsignal.

According to this second aspect, the present invention more specificallyaims at providing a low-consumption circuit operating under a lowvoltage and which is easily integrable.

Conventionally, to generate a voltage pulse from a logic signal,capacitors are used. A disadvantage is that these capacitors aredifficult to integrate or, to at the very least, occupy a significantspace in the integrated circuit.

To achieve these and other objects, the present invention provides aswitching circuit adapted to generating a pulse upon occurrence of arising edge of a signal applied on an input terminal, including:

a first NPN-type bipolar transistor having its emitter connected to theinput terminal;

a second transistor having a control electrode connected, by a firstresistor, to the input terminal, the base of the first transistor beingconnected to a supply voltage by the second transistor in series with asecond resistor; and

a third transistor connecting an output terminal of the switchingcircuit to a reference voltage and having a control electrode connectedto the collector of the first transistor.

According to an embodiment of the present invention, the first andsecond transistors are on in the quiescent state, while the thirdtransistor is off in the quiescent state.

According to an embodiment of the present invention, the pulse durationis determined by the time taken by the second transistor to turn offthrough the base-collector junction of the first forward-biasedtransistor and temporarily turning on the third transistor.

According to an embodiment of the present invention, the first resistortakes part in the setting of the pulse duration.

According to an embodiment of the present invention, the secondtransistor is a bipolar PNP-type transistor.

According to an embodiment of the present invention, the thirdtransistor is a bipolar NPN-type transistor.

The present invention also provides a logic circuit that provides anon-inverting function, including:

a bipolar PNP type input transistor having its emitter connected, by abiasing resistor, to a terminal of application of a positive voltage andhaving its base connected, by an input resistor, to a terminal ofapplication of a logic signal;

a bipolar NPN type output transistor having its emitter connected to aterminal of application of a reference voltage, having its baseconnected to the collector of the input transistor and its collectorforming an output terminal of the logic circuit connected, by an outputresistor, to the terminal of application of the positive voltage; and

a switching circuit having its output terminal connected to the base ofthe output transistor to accelerate its desaturation, the input terminalof the switching circuit being connected to the input terminal of thelogic circuit.

According to an embodiment of the present invention, the second resistoris connected between the first transistor and the terminal ofapplication of the positive voltage, the collector of the firsttransistor being directly connected to the base of the secondtransistor.

The present invention further provides a generator of pulses from avoltage square pulse applied on an input terminal, including a switchingcircuit having its output terminal forming an output terminal of thepulse generator connected, by a resistor, to a terminal of applicationof the most positive voltage.

According to an embodiment of the present invention, the collector ofthe first transistor is connected to the base of the second transistorby the second resistor conditioning the pulse duration.

The foregoing objects, features and advantages of the present invention,will be discussed in detail in the following non-limiting description ofspecific embodiments in connection with the accompanying drawings, inwhich:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the conventional symbol of a logic circuit to which thepresent invention according to its first aspect applies;

FIG. 2 shows the detailed electric diagram of a conventional logiccircuit fulfilling a non-inverting function;

FIGS. 3A and 3B illustrate the operation of the conventional circuit ofFIG. 2;

FIG. 4 partially shows in the form of blocks an embodiment of a logiccircuit fulfilling a non-inverting function according to the firstaspect of the present invention;

FIG. 5 shows a first embodiment of a switching circuit according to thepresent invention;

FIG. 6 shows the detailed electric diagram of an embodiment of the logiccircuit of FIG. 4;

FIGS. 7A to 7I illustrate, by timing diagrams, the dynamic operation ofthe circuit of FIG. 6;

FIG. 8 shows a second embodiment of a switching circuit according to thepresent invention;

FIG. 9 shows an embodiment of a pulse generation circuit according tothe second aspect of the present invention; and

FIGS. 10A and 10B illustrate, in the form of timing diagrams, theoperation of the circuit of FIG. 9.

DETAILED DESCRIPTION

The same elements have been designated by same references in thedifferent drawings. For clarity, the timing diagrams of FIGS. 3, 7 and10 are not to scale.

FIG. 4 shows a logic circuit 10 that provides a non-inverting functionaccording to the first aspect of the present invention.

As previously, such a logic circuit 10 includes two supply terminals 2,3. Terminal 2 is connected to a more positive voltage VDD. Terminal 3 isconnected to a more negative voltage GND, for example, the ground. Aninput terminal 4 is intended for receiving a logic signal IN. An outputterminal 5 is intended for providing a logic signal OUT corresponding toinput signal IN. As previously still, an output branch of circuit 10includes, in series between terminals 2 and 3, a resistor Rn and anNPN-type bipolar transistor TN1. The emitter of transistor TN1 isconnected to ground terminal 3. Its collector is connected to terminal5. The base of transistor TN1 is, as previously, connected to thecollector of a PNP-type transistor TP1 having its emitter connected, bya biasing resistor Rp1, to terminal 2. The base of transistor TP1 isconnected, by an input resistor Re1, to terminal 4. All the precedingstructure corresponds to the electric diagram of a conventional circuit(1, FIG. 2).

A feature of the present invention is to provide a switching circuit 20for forcing the desaturation of output transistor TN1 and thus helpingthe switching of logic circuit 10. Circuit 20 includes a switch Kconnecting the base of transistor TN1 to ground 3 and a circuit 21 forcontrolling switch K. Circuit 21 includes a control terminal CTRL whichis connected to input terminal 4 of circuit 10 receiving the logiccircuit to be processed.

The function of control circuit 21 is to generate a turn-on pulse forswitch K upon each rising edge of input signal IN. A pulse control hasseveral advantages.

First, the circuit operation in a switching to the low state isdissociated from its operation in a switching to the high state. For aswitching to the low state, the circuit operation is not modified,switch K remaining off. A sufficient base current to properly saturatethe input stage can thus be provided. For a switching to the low state,the controlled turning-on of switch K enables controlling thedesaturation of transistor TN1, and thus the switching speed,independently from the speed of switching to the high state.

Further, in static operation, any power consumption is avoided in theinput stage (transistor TP1) when the input signal is high.

According to the present invention, a turn-on pulse duration of switch Kwhich is sufficient to help the desaturation not only of transistor TN1upon a switching to the low state, but also of transistor TP1, isprovided.

FIG. 5 shows a first embodiment of a switching circuit 20 according tothe present invention. Control circuit 21 is here formed of a PNP-typetransistor TP2 and of an NPN-type transistor TN2. The emitter oftransistor TP2 is connected to voltage VDD by a biasing resistor Rp2.The base of transistor TP2 is connected, by a resistor Re2, to input orcontrol terminal CTRL of circuit 21. The collector of transistor TP2 isconnected to the base of transistor TN2. The emitter of transistor TN2is connected to terminal CTRL and its collector provides the outputsignal of block 21.

In the example of FIG. 5, switch K is formed of an NPN-type transistorTN3 having its base connected to the collector of transistor TN2 andhaving its emitter connected to ground GND. The collector of transistorTN3 forms an output terminal 22 of switching circuit 20.

The operation of the switching circuit of FIG. 5 will be discussedhereafter in relation with its application in a logic circuit such asillustrated in FIG. 4.

FIG. 6 shows the detailed electric diagram of such a circuit. It showsthe components of the logic circuit discussed in relation with FIG. 4 aswell as the components of the switching circuit of FIG. 5. Inputterminal 4 is connected to resistors Re1 and Re2 and to the emitter oftransistor TN2. Terminal 22 of circuit 20 (collector of transistor TN3)is connected to the collector of transistor TP1 and to the base oftransistor TN1. The emitter of transistor TN3 is connected to terminal 3and resistor Rp2 is connected to terminal 2. It should be noted that theassembly of transistor TP2 is close to that of transistor TP1. The twotransistors receive the input signal via an input resistor and arebiased by their respective emitters to voltage VDD.

In static operation, the operation of a non-inverting logic circuit isrespected.

Assume an input IN at the high state. Transistor TP1 is then off.Transistor TN1 can receive no base current and is thus also off. SignalOUT then is high. On the side of switching circuit 20, transistor TP2 isoff. Transistor TN2 receives no base current and is thus also off, andso is transistor TN3. This results in no power consumption in controlcircuit 20 when the circuit is, in static operation, at the high state.The general circuit power consumption is then limited to the powerconsumption in resistor Rn. The power consumption of a conventionallogic circuit of this type (FIG. 2) is thus respected.

Now assume that input IN is low. In this case, in static operation,transistor TP1 is on. On the side of switching circuit 20, transistorTP2 is biased to be on. The base-emitter junction of transistor TN2 isforward biased and receives a base current. However, since no currentcan be drawn from the collector of transistor TN2 (the base oftransistor TN3), its collector-emitter voltage is minimum (a few tens ofmV). Accordingly, the low level is substantially transferred onto thebase of transistor TN3, which confirms its off state. Since switch TN3is off, transistor TN1 is turned on by the turning-on of transistor TP1.Output 5 accordingly is low. In the low state, the logic circuit powerconsumption corresponds to the dissipation in biasing resistors Rp1 andRp2 and in input resistors Re1 and Re2.

In the assembly of FIG. 6, the function of transistor TN3 is toaccelerate the desaturation of transistor TN1 when off. For thispurpose, transistor TN3 is turned on when input signal IN switches high.However, to prevent the continuous power consumption of the assembly,transistor TN3 must be turned back off after a short period havingenabled desaturation of transistor TN2. This is the function of circuit21.

FIGS. 7A to 7I illustrate, in timing diagrams, the dynamic operation ofthe circuit of FIG. 6 upon switching of input signal IN from the lowstate to the high state. FIG. 7A shows the course of input voltage IN.FIGS. 7B to 7H show the courses of currents Ib1, Ib2, Ic2, Ib3, Id, Ic1,and Ie2 in, respectively, the base of transistor TP1, the base oftransistor TP2, the collector of transistor TP2 (and thus the base oftransistor TN2), the base of transistor TN3 (and thus the collector oftransistor TN2), the base of transistor TN1, the collector of transistorTP1, and the emitter of transistor TN2. FIG. 7I shows the course ofoutput voltage OUT. The directions taken for the drawing of the currentsin FIGS. 7B to 7H are shown in FIG. 6.

Initially, signals IN and OUT are low. Transistors TP1, TP2, TN1, andTN2 are thus on. Accordingly, positive base currents Ib1, Ib2, and Idflow through transistors TP1 and TP2 (coming out of the bases) and intotransistor TN1 (coming into the base). Positive collector currents Ic1and Ic2 flow through transistors TP1 and TP2 (coming out of thecollectors). Finally, a positive emitter current (coming out of theemitter) flows in transistor TN2.

A switching of signal IN is assumed from a time t10. The switching ofsignal IN lasts until a time t11 when the voltage reaches the high level(for example, VDD). Interval t10-t11 generally is on the order of 0.1μs. Between times t10 and t11, base currents Ib1 and Ib2 decrease untilreaching negative values I1 and I2, for which transistors TP1 and TP2desaturate. Values I1 and I2 depend on the transistor sizes and on thevalues of resistances Re1 and Re2, respectively. The durations (timest11 to t12 and t11 to t13, respectively) for which values I1 and I2 aremaintained depend on the time taken by transistors TP1 and TP2 todesaturate. From time t12 for transistor TP1 and from time t13 fortransistors TP2, base currents Ib1 and Ib2 tend towards zero. They annulat times t14 and t15 when transistors TP1 and TP2 are respectively off.

On the side of transistor TP2, its turning off comes along with anevacuation of the charges of its collector, and thus with a decrease inits collector current. The evacuation of these charges occurs throughthe base-collector junction of transistor TN2, which is thus forwardbiased. Indeed, transistor TN3 being initially off, its base (and thusthe collector of transistor TN2) is at a voltage smaller thanapproximately 0.6 V. Now, as long as transistor TP2 is not off, the baseof transistor TN2 is drawn towards voltage VDD (neglecting the voltagedrop in resistor Rp2).

The current which is then injected into the base of transistor TN3 issufficient to turn it on at a time t16 very close to time t10 (forexample, a few tens of nanoseconds after time t10). From time t16,transistor TN3 being on, the base of transistor TN1 and the collector oftransistor TP1 are drawn towards the ground. For transistor TN1, thistranslates as an abrupt desaturation during which its base current Idbecomes very negative until a time t17 when it annuls, all chargeshaving been evacuated. For transistor TP1, this translates as a shift inthe shape of its collector current. Between times t10 and t16, thecharges of the collector of transistor TP1 evacuate through the base oftransistor TN1, that is, relatively slowly. From time t16, the collectorcurrent strongly increases until reaching, at time t17, a maximum valueI3. Value I3 depends on the gain of transistor TP1 and on value I1 ofits base current.

From time t17, transistor TN3 absorbs the desaturation of transistorTP1, but transistor TN1 is off. Accordingly, voltage OUT startsincreasing until a time t18 when it reaches level VDD. On the side oftransistor TP1, the collector current remains at value I3 until timet12, then decreases to annul at time t14 when all the collector chargeshave been evacuated.

Time interval t17-t18 is independent from the circuit of the presentinvention. It depends on the charge connected on terminal 5. Inapplications concerning the present invention, interval t17-t18generally is shorter than one microsecond. However, while thedesaturation of transistor TN1 takes approximately 1 μs in aconventional circuit, this duration is, due to the present invention,brought down to a few tens of nanoseconds (less than 0.1 μs). Thisduration is adjusted by the value of resistor Re2.

Transistor TN3 remains on as long as transistor TP2 is not off, that is,as long as its has not absorbed, through its base, all the collectorcharges of transistor TP2. From time t15, transistor TN3 is off, sinceno further current can be injected onto its base.

Between times t10 and t16, emitter current Ie2 of transistor TN2switches from a positive value I4 to a very low negative value (leakagecurrent in the reverse-biased base-emitter junction), then decreasesfrom time t13, to annul at time t15. Value I4 substantially correspondsto the value of current Ic2 evacuated by the emitter when transistor TN2is on.

Between times t10 and t11, current Ic2 increases from value I4 to avalue I6, before annulling between times t13 and t15. Value I6 dependson the gain of transistor TP2 and on value I2.

The conduction duration of transistor TN3 essentially depends on thetime taken by transistor TP2 to desaturate into transistor TN2.Accordingly, this duration depends on the size of transistor TP2 (on itsemitter surface area) and on its saturation level, and thus on the valueof resistor Re2.

In the circuit sizing, it will be ascertained that transistor TP2 takeslonger to turn off than transistor TP1 . Otherwise, transistor TN1 risksbeing turned by on at the turning-off of transistor TN3. In a specificexample of embodiment where transistors TP2 and TP1 have identical sizesand identical biasings, resistance Re2 may be sized to correspond totwice the value of resistance Re1.

When the input signal switches from the high state to the low state,transistor TP1 is conventionally turned on (saturated). Since transistorTN3 is off, transistor TN1 is turned on. The switching speed is notaltered by the implementation of the present invention. Conversely,since transistor TN1 can now be rapidly desaturated, the base currentcan be increased to turn it on and thus also increase the switching fromthe high state to the low state. On the switching circuit side,transistor TP2 is properly biased to be on, and so is transistor TN2.However, since transistor TN2 cannot draw a base current from transistorTN3, the off state of transistor TN3 is confirmed.

The minimum circuit supply voltage is determined by the maximum voltagebetween the sum of the base-collector voltage of transistor TN1 and ofthe collector-emitter voltage of transistor TP1 and the sum of thebase-emitter voltage of transistor TN2, of the collector-emitter voltageof transistor TP2, and of level IN in the low state.

The shown connection of transistor TP2 implies that input terminal 4 isconnected to a current output type circuit (open collector). Thespecific assembly of transistor TP2 is a precaution to avoid favoringthe parasitic thyristor that it forms with transistor TN2. In the casewhere terminal 4 is connected to a circuit having a voltage output, thisproblem is not posed since the voltages are imposed. Transistor TP2 canthus be inverted (emitter connected to the base of transistor TN2 andcollector connected to resistor Rp2).

An advantage of the present invention according to its first aspect isthat it considerably increases the switching speed of the non-invertinglogic circuit.

Another advantage of the present invention is that this speed isobtained neither at the detriment of the power consumption, nor at thedetriment of the supply voltage.

More generally, an advantage of the switching circuit according to thepresent invention is that it provides an integrable solution forgenerating pulses of predetermined duration.

FIG. 8 shows a second embodiment of a switching circuit 20′ according tothe present invention. This embodiment is different from that of FIG. 5essentially in that it uses a MOS transistor to form transistor K. It isa P-channel MOS transistor P3 having its gate connected to the collectorof bipolar transistor TN2. A resistor R3 connects the gate of MOStransistor P3 to its grounded source to be used as a current-to-voltageconverter, to temporarily turn on transistor P3 by the desaturating oftransistor TN2.

However, the use of a bipolar technology is a preferred embodiment ofthe present invention since it is less expensive and less sensitive toelectromagnetic disturbances.

FIG. 9 shows the electric diagram of a pulse generator circuit 30according to a second aspect of the present invention. The switchingcircuit of the present invention here is used to generate a pulse, on anoutput terminal 31, upon each rising edge of a logic signal introducedon an input terminal 32. Generator 30 includes transistor TN2 having itsbase connected to transistor TN3, the collector of which provides thepulse signal and the emitter of which is connected to ground terminal 3.The base of transistor TN2 is connected to transistor TP2 by a resistorRd. The emitter of transistor TP2 here is directly connected to terminal2 of application of supply voltage VDD. The base of transistor TP2 isconnected, by resistor Re2, to input terminal 32. In this aspect of thepresent invention, the collector of transistor TN3 is connected toterminal 2 by a resistor R3. To provide a pulse of same sign as theinput signal, stage R3-TN3 of circuit 30 is reproduced on an outputbranch forming an inverter. Accordingly, the collector of transistor TN3is connected to the base of an NPN-type transistor TN4. The emitter oftransistor TN4 is connected to terminal 3. Its collector is connected toterminal 31 and, via a resistor R4, to terminal 2.

The operation of the pulse generator of FIG. 9 is illustrated by FIGS.10A and 10B, which show, in the form of timing diagrams, an example ofgeneration of a pulse based on a state switching of an input signal VIN.

Assume that at a time t20, signal VIN (FIG. 10A) applied on terminal 32switches from the low state to the high state (VDD). Transistor TP2 isturned off by the disappearing of its base-emitter voltage. TransistorTN2, the emitter of which also receives signal Vin, also turns off. Thebase-collector junction of transistor TN2 is then used to desaturatetransistor TP2 in resistor Rd. This turns on transistor TN3 and turnsoff transistor TN4. The output switches high. This state is maintainedfor the time necessary to desaturate transistor TP2. At a time t21 wheretransistor TP2 is assumed to have ended its desaturation into the baseof transistor TN2, said transistor turns off, which turns off transistorTN3 and causes the switching of the output.

The pulse generator of the present invention only generates a pulse onthe rising edges of the input signal. As discussed in relation with thefirst aspect of the present invention, transistor TN3 remains off uponoccurrence of a falling edge (time t22).

The duration of the generated pulse depends on the saturation oftransistor TP2, which is a function of the value of resistance Re2. Thehigher this value, the lighter the saturation and the shorter thedesaturation time. Resistor Rd is thus used to limit the collectorcurrent of transistor TP2. It thus also takes part in the duration ofthe output pulse. A generator according to the present invention can besized, by remaining integrable, for a pulse duration of approximately 10μs.

According to an alternative not shown, transistor TP2 may be replacedwith a P-channel MOS transistor to slow the desaturation down, providedto always use a bipolar transistor, the base-collector junction of whichis used to temporarily turn on the output transistor desaturationswitch.

An advantage of the pulse generator illustrated in FIG. 9 is that itavoids use of capacitors to generate a pulse from a voltage squarepulse. Even with a resistance Re2 on the order of some hundred kiloohms, the occupied space is lesser than that of a capacitor on the orderof 10 picofarads that it would be necessary to provide to obtain a pulseof a few microseconds.

Another advantage of the pulse generator according to the presentinvention is that it has a low power consumption. In its quiescentstate, the power consumption is essentially due to the emitter currentof transistor TN2, and thus is a function of the value of resistor Rdproviding the base current of this transistor. The current in resistorRe2 is negligible since it corresponds to the base current of transistorTP2. The power consumption of the generator of the present invention isvery low as compared, for example, to that of a one-shot circuit, whichis another conventional means of pulse generation.

Of course, the present invention is likely to have various alterations,modifications, and improvements which will readily occur to thoseskilled in the art. In particular, the sizing of the transistors andresistors is within the abilities of those skilled in the art based onthe functional indications given hereabove and on the application.Further, although the present invention has been discussed in relationwith the generation of positive pulses, its transposing to a negativepulse generation is within the abilities of those skilled in the art.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

1. A switching circuit capable of generating a pulse upon occurrence ofa rising edge of a signal applied on an input terminal, including: afirst NPN-type bipolar transistor having its emitter connected to theinput terminal; a second transistor having a control electrodeconnected, by a first resistor, to the input terminal, a base of thefirst transistor being connected to a supply voltage by the secondtransistor in series with a second resistor; and a third transistorconnecting an output terminal of the switching circuit to a referencevoltage and having a control electrode connected to a collector of thefirst transistor.
 2. The switching circuit of claim 1, wherein the firstand second transistors are on in a quiescent state, while the thirdtransistor is off in the quiescent state.
 3. The switching circuit ofclaim 1 or 2, wherein a pulse duration is determined by a time taken bythe second transistor (TP2) to turn off through the base-collectorjunction of the first forward-biased transistor and temporarily turningon the third transistor.
 4. The switching circuit of claim 1, whereinthe pulse duration is set by the first resistor.
 5. The switchingcircuit of claim 1, wherein the second transistor is a bipolar PNP-typetransistor.
 6. The switching circuit of claim 1, wherein the thirdtransistor is a bipolar NPN-type transistor.
 7. A logic circuit thatprovides a non-inverting function, including: a bipolar PNP type inputtransistor having its emitter connected, by a biasing resistor, to aterminal of application of a positive voltage and having a baseconnected, by an input resistor, to an input terminal of a logic signal;a bipolar NPN type output transistor having an emitter connected to aninput terminal of a reference voltage, having base connected to acollector of the input transistor and a collector forming an outputterminal of the logic circuit connected, by an output resistor, to theterminal receiving the positive voltage; and including the switchingcircuit of claim 1, the output terminal of the switching circuit beingconnected to a base of the output transistor to accelerate itsdesaturation, the input terminal of the switching circuit beingconnected to the input terminal of the logic circuit.
 8. The logiccircuit of claim 7, wherein the second resistor is connected between thefirst transistor and the terminal receiving the positive voltage, thecollector of the first transistor being directly connected to the baseof the second transistor.
 9. A generator of pulses from a voltage squarepulse applied on an input terminal, including the switching circuit ofclaim 1, having its output terminal forming an output terminal of thepulse generator connected, by a resistor, to a terminal of applicationof the most positive voltage.
 10. The pulse generator of claim 9,wherein the collector of the first transistor is connected to the baseof the second transistor by the second resistor conditioning the pulseduration.